The present invention relates to a method of manufacturing a semiconductor integrated circuit device (or semiconductor device), for example, a method applicable to a semiconductor integrated circuit device having a high breakdown voltage transistor.
Japanese Unexamined Patent Application Publication No. 2011-187530 (Patent Document 1) or U.S. Patent Publication No. 2011-215423 (Patent Document 2) corresponding thereto relates to a CMOS (complementary metal-oxide-semiconductor) semiconductor integrated circuit. Disclosed herein is a technology of forming a trench in the surface of a semiconductor substrate and thereby providing an insulated gate FET (field effect transistor) having a high drain current. This document discloses, for example, a MOSFET having a trench extending beneath a gate from a source contact region to a drain contact region.
Japanese Unexamined Patent Application Publication No. 2012-18973 (Patent Document 3) or U.S. Patent Publication No. 2012-7151 (Patent Document 4) corresponding thereto relates to a CMOS semiconductor integrated circuit having integrated high breakdown voltage transistors. Disclosed herein is a high breakdown voltage MIS (metal-insulator-semiconductor) FET having a trench or the like running parallel to or perpendicular to a channel direction in a channel region or the like.
Japanese Unexamined Patent Application Publication No. 2011-66067 (Patent Document 5) or U.S. Patent No. 2012-8692352 (Patent Document 6) corresponding thereto relates to a CMOS semiconductor integrated circuit having high breakdown voltage lateral transistors integrated therein. Disclosed herein is a CMOS semiconductor integrated circuit in which high breakdown voltage lateral MOSFETs are isolated from each other by a DTI (deep trench isolation) or the like.